As data processing communication systems have expanded to incorporate multiple processors that share a common core of memory or common input/output (I/O) devices, the performance associated with the communication system must be continually improved to allow for greater data processing capacity and faster speeds. In an attempt to optimize performance of the data processing communication system, many techniques have been developed to implement communication between multiple data processors and core memory or input/output devices.
One such technique implements a shared memory bus to allow a plurality of data processors to access a memory. When a shared memory bus is implemented, an arbitration operation, which utilizes separate signals for requesting and acknowledging control of the shared bus, is required to determine which of the plurality of data processors will access the memory at a given time. While arbitration is a useful methodology for allowing data processors to communicate with shared devices in a communication system, arbitration implementations require a significant amount of overhead, both in time and circuit costs. For example, the time required to perform the arbitration function must necessarily be factored into a total time required for the data processor to communicate with the memory. Additionally, such arbitration operations must be implemented using logic circuitry which adds additional overhead costs to the entire system.
In data processing communication systems which do not tolerate the time consumption associated with an arbitration scheme, a dedicated, rather than shared, memory bus is implemented for each data processor. This dedicated memory bus connects each of the data processors to the common memory or input/output device. However, because this approach requires separate busses for each data processor, it is costly and complicated. Therefore, it is typically used in specialized applications having specified and rigid standards.
In other high performance data communication systems, a switch architecture is implemented to allow a data processor to communicate with the shared memory or input/output devices without the use of a shared bus or a dedicated bus. In a switch architecture, a first data processor communicates with a first input/output device and a second data processor communicates with a first memory in parallel because each data processor can be switched to a unique path. However, when both the first and second data processor want to communicate with the same memory device, latency is introduced in the switching architecture as these operations may not be performed in parallel because a single unique path is desired to be used by both data processors. In this instance, latency is introduced during an ensuing arbitration operation which establishes which of the data processor and the memory or other device has access to the unique data path.
While prior art techniques effectively allow multiple data processors to communicate with a shared resource, it is desirable to have a system which minimizes a latency associated with determining whether or when such communication operations should take place. Therefore, it is desirable to have a data communication system which minimizes such latency and optimizes the data communication system for efficient performance.